Field of the Invention
The invention relates to an integrated memory having a self-repair function.
To repair faulty memory cells, integrated memories have redundant word lines or redundant bit lines. These redundant lines can replace regular lines with faulty cells on an address basis. It is known practice to test integrated memories via their external connections using external testing devices and then to program the redundant elements externally using a laser beam. The redundancy circuit then has programmable elements in the form of laser fuses which are used to store the address of a line which is to be replaced. The laser fuses are electrical connection elements which can be severed at the end of the production process for the integrated memory using the laser beam. This methodv requires an external testing device for carrying out the memory cell test. It also has the disadvantage that the signals needed to carry out the test have to be transmitted via the external connections of the memory, which are restricted in number. This means that the bandwidth of the test signals is limited and such a test takes a relatively long time.
A memory having a self-repair function is disclosed in U.S. Pat. No. 5,313,424 to Adams et al. A self-test unit tests the memory cells in the memory and then stores the address of defective word lines in an appropriate address register. The memory is then supplied externally with an activation signal having a high potential level, and severable electrical connection elements (fuses), which are component parts of a redundancy circuit, are then destroyed to code the faulty word addresses stored in the address register. The fuses are destroyed with a high current that causes them to melt.
The self-test described in U.S. Pat. No. 5,313,424 for the memory with subsequent self-repair has the advantage that no external testing device is needed to carry out the memory cell test, and that the bandwidth for the test signals is not limited by the number of external connections of the memory. However, the results of the memory cell test, i.e. the addresses of the faulty word lines, remain "hidden" in the integrated memory. Accordingly, analysis of the faults which occur, which is of interest to the manufacturer of the memory, is not possible.